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? freescale semiconductor, inc., 2004. all rights reserved. this document contains information on a new product. specifications and information herein are subject to change without notice. freescale semiconductor advance information MR2A16A/d rev. 0.1, 7/2004 256k x 16-bit 3.3-v asynchronous magnetoresistive ram introduction the MR2A16A is a 4,194,304-bit magnetoresistive random access memory (mram) device organized as 262,144 words of 16 bits. the MR2A16A is equipped with chip enable (e ), write enable (w ), and output enable (g ) pins, allowing for significant system design flexibility without bus contention. because the MR2A16A has separate byte-enable controls (lb and ub ), individual bytes can be written and read. mram is a nonvolatile memory technology that protects data in the event of power loss and does not require periodic refreshing. the MR2A16A is the ideal memory solution for applications that must permanently store and retrieve critical data quickly. the MR2A16A is available in a 400-mil, 44-lead plastic small-outline tsop type-ii package with an industry-standard center power and ground sram pinout. features ? single 3.3-v power supply commercial temperature range (0c to 70c) symmetrical high-speed read and write with fast access time (25 ns) flexible data bus control ? 8 bit or 16 bit access equal address and chip-enable access times automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss all inputs and outputs are transistor-transistor logic (ttl) compatible fully static operation full nonvolatile operation with 10 years minimum data retention
MR2A16A/d, rev. 0.1 2 freescale semiconductor device pin assignment figure 1. block diagram device pin assignment figure 2. MR2A16A in 44-pin tsop type ii package upper byte output enable lower byte output enable column decoder row decoder 256k x 16 bit memory array final write drivers sense amps upper byte write enable lower byte write enable output enable buffer chip enable buffer write enable buffer byte enable buffer address buffers upper byte output buffer lower byte output buffer upper byte write driver lower byte write driver dql[7:0] dqu[15:8] g e w ub lb 8 10 8 8 8 8 16 16 18 a[17:0] 8 8 8 8 ub lb 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a15 a14 a13 g ub lb dqu15 dqu14 dqu13 dqu12 v ss v dd dqu11 dqu10 dqu9 dqu8 nc a9 a8 a7 a6 a5 a16 a17 a10 a11 a12 e dql0 dql1 dql2 dql3 v dd v ss dql4 dql5 dql6 dql7 w a0 a1 a2 a3 a4 table 1. pin functions signal name function a[17:0] address input e chip enable w write enable g output enable ub upper byte select lb lower byte select dql[7:0] data i/o, lower byte dqu[15:8] data i/o, upper byte v dd +3.3-v power supply v ss ground nc do not connect this pin
electrical specifications MR2A16A/d, rev. 0.1 freescale semiconductor 3 electrical specifications absolute maximum ratings this device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (hi-z) circuits. the device also contains protection against external magnetic fields. precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. table 2. operating modes e g w lb ub mode v dd current dql[7:0] dqu[15:8] hxxxxnot selected i sb1 , i sb2 hi-z hi-z l h h x x output disabled i dda hi-z hi-z l x x h h output disabled i dda hi-z hi-z l l h l h lower byte read i dda d out hi-z l l h h l upper byte read i dda hi-z d out l l h l l word read i dda d out d out l x l l h lower byte write i dda d in hi-z l x l h l upper byte write i dda hi-z d in lxlllword write i dda d in d in notes: 1. h = high, l = low, x = don?t care 2. hi-z = high impedance table 3. absolute maximum ratings parameter symbol value unit supply voltage v dd ?0.5 to 4.6 v voltage on any pin v in ?0.5 to v dd + 0.5 v output current per pin i out 20 ma package power dissipation p d tbd w temperature under bias t bias ?10 to 85 c storage temperature t stg ?55 to 150 c lead temperature during solder (3 minute max) t lead 235 c maximum magnetic field at package surface h max 20 oe notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating conditions. exposure to excessive voltages or magnetic fields could affect device reliability. 2. all voltages are referenced to v ss . 3. power dissipation capability depends on package characteristics and use environment.
MR2A16A/d, rev. 0.1 4 freescale semiconductor electrical specifications direct current (dc) table 4. operating conditions parameter symbol min typ max unit power supply voltage v dd 3.0 (1) notes: 1. after power up or if v dd falls below v wi , a waiting period of 1 s must be observed. memory is designed to prevent writing for all input pin conditions if v dd falls below minimum v wi . 3.3 3.6 v write inhibit voltage v wi 2.5 2.7 3.0 (1) v input high voltage v ih 2.2 ? v dd + 0.3 (2) 2. v ih (max) = v dd + 0.3 vdc; v ih (max) = v dd + 2.0 vac (pulse width 10 ns) for i 20.0 ma. v input low voltage v il ?0.5 (3) 3. v il (min) = ?0.5 vdc; v il (min) = ?2.0 vac (pulse width 10 ns) for i 20.0 ma. ?0.8v operating temperature t a 070c table 5. dc characteristics parameter symbol min typ max unit input leakage current i lkg(i) ?? 1 a output leakage current i lkg(o) ?? 1 a output low voltage (i ol = +4 ma) (i ol = +100 a) v ol ? ? 0.4 v ss + 0.2 v output high voltage (i oh = ?4 ma) (i oh = ?100 ma) v oh 2.4 v dd ? 0.2 ??v table 6. power supply characteristics parameter timing set symbol typ max unit ac active supply current ? read modes (i out = 0 ma, v dd = max) 20 i ddr tbd tbd ma 25 i ddr tbd tbd ma 35 i ddr tbd tbd ma ac active supply current ? write modes (v dd = max) 20 i ddw tbd tbd ma 25 i ddw tbd tbd ma 35 i ddw tbd tbd ma ac standby current (v dd = max, e = v ih ) (no other restrictions on other inputs) 20 i sb1 tbd tbd ma 25 i sb1 tbd tbd ma 35 i sb1 tbd tbd ma cmos standby current (e v dd ? 0.2 v and v in v ss + 0.2 v or v dd ? 0.2 v) (v dd = max, f = 0 mhz) i sb2 tbd tbd ma
electrical specifications MR2A16A/d, rev. 0.1 freescale semiconductor 5 figure 3. output load for ac test table 7. capacitance parameter symbol typ max unit address input capacitance c in ?6pf control input capacitance c in ?6pf input/output capacitance c i/o ?8pf notes: 1. (f = 1.0 mhz, dv = 3.0 v, t a = 25c, periodically sampled rather than 100% tested) table 8. ac measurement conditions parameter value logic input timing measurement reference level 1.5 v logic output timing measurement reference level 1.5 v logic input pulse levels 0 or 3.0 v input rise/fall time 2 ns output load for low and high impedance parameters see figure 3a output load for all other timing parameters see figure 3b ab output r l = 50 ? v l = 1.5 v z d = 50 ? output 600 ? 725 ? 5 pf +3.3 v
MR2A16A/d, rev. 0.1 6 freescale semiconductor timing specifications timing specifications read mode table 9. read cycle timing (see notes 1 and 2) parameter symbol timing set unit notes 20 25 35 min max min max min max read cycle time t avav 20 ? 25 ? 35 ? ns address access time t avqv ?20?25?35 ns enable access time t elqv ?20?25?35 ns 3 output enable access time t glqv ?10?11?15 ns byte enable access time t blqv ?10?11?15 ns output hold from address change t axqx 3?3?3?ns enable low to output active t elqx 3?3?3?ns4, 5 output enable low to output active t glqx 0?0?0?ns4, 5 byte enable low to output active t blqx 0?0?0?ns4, 5 enable high to output hi-z t ehqz 0 10 0 11 0 15 ns 4, 5 output enable high to output hi-z t ghqz 0607010ns4, 5 byte high to output hi-z t bhqz 0607010ns4, 5 notes: 1. w is high for read cycle. 2. due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. addresses valid before or at the same time e goes low. 4. this parameter is sampled and not 100% tested. 5. transition is measured 200 mv from steady-state voltage.
timing specifications MR2A16A/d, rev. 0.1 freescale semiconductor 7 figure 4. read cycle 1 figure 5. read cycle 2 t avav t axqx t avqv data valid previous data valid q (data out) a (address) notes: 1. device is continuously selected (e v il , g v il ). t avav t avqv a (address) t elqx t glqv data valid e (chip enable) g (output enable) lb , ub (byte enable) q (data out) t elqv t glqx t blqv t blqx t bhqz t ghqz t ehqz
MR2A16A/d, rev. 0.1 8 freescale semiconductor timing specifications write mode table 10. write cycle timing 1 (w controlled; see notes 1, 2, 3, and 4) parameter symbol timing set unit notes 20 25 35 min max min max min max write cycle time t avav 20 ? 25 ? 35 ? ns 8 address set-up time t avwl 0?0?0?ns address valid to end of write (g high) t avwh 12 ? 15 ? 18 ? ns address valid to end of write (g low) t avwh 15 ? 17 ? 20 ? ns write pulse width (g high) t wlwh t wleh 8 ? 10 ? 15 ? ns write pulse width (g low) t wlwh t wleh 8 ? 10 ? 15 ? ns data valid to end of write t dvwh 5?6?10?ns data hold time t whdx 0?0?0?ns write low to data hi-z t wlqz 0709012ns5, 6, 7 write high to output active t whqx 3?3?3?ns5, 6, 7 write recovery time t whax 8 ? 10 ? 12 ? ns notes: 1. a write occurs during the overlap of e low and w low. 2. due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. if g goes low at the same time or after w goes low, the output will remain in a high-impedance state. 4. after w , e , or ub /lb has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. this parameter is sampled and not 100% tested. 6. transition is measured 200 mv from steady-state voltage. 7. at any given voltage or temperature, t wlqz max < t whqx min. 8. all write cycle timings are referenced from the last valid address to the first transition address.
timing specifications MR2A16A/d, rev. 0.1 freescale semiconductor 9 figure 6. write cycle 1 (w controlled) t avav t avwh a (address) t wleh data valid e (chip enable) w ( write enable) lb , ub (byte enable) q (data out) t dvwh t wlqz t whdx d (data in) t whax hi-z hi-z t avwl t wlwh t whqx
MR2A16A/d, rev. 0.1 10 freescale semiconductor timing specifications table 11. write cycle timing 2 (e controlled; see notes 1,2,3, and 4) parameter symbol timing set unit notes 20 25 35 min max min max min max write cycle time t avav 20 ? 25 ? 35 ? ns 7 address set-up time t avel 0?0?0? ns address valid to end of write (g high) t aveh 12 ? 15 ? 18 ? ns address valid to end of write (g low) t aveh 15 ? 17 ? 20 ? ns enable to end of write (g high) t eleh t elwh 8 ? 10 ? 15 ? ns enable to end of write (g low) t eleh t elwh 8 ? 10 ? 15 ? ns 5, 6 data valid to end of write t dveh 5?6?10? ns data hold time t ehdx 0?0?0? ns write recovery time t ehax 8 ? 10 ? 12 ? ns notes: 1. a write occurs during the overlap of e low and w low. 2. due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. if g goes low at the same time or after w goes low, the output will remain in a high-impedance state. 4. after w , e , or ub /lb has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. if e goes low at the same time or after w goes low, the output will remain in a high-impedance state. 6. if e goes high at the same time or before w goes high, the output will remain in a high-impedance state. 7. all write cycle timings are referenced from the last valid address to the first transition address.
timing specifications MR2A16A/d, rev. 0.1 freescale semiconductor 11 figure 7. write cycle 2 (e controlled) t avav t aveh a (address) data valid e (chip enable) w (write enable) lb , ub (byte enable) q (data out) d (data in) t ehax hi-z t eleh t dveh t avel t elwh t ehdx
MR2A16A/d, rev. 0.1 12 freescale semiconductor timing specifications table 12. write cycle timing 3 (lb /ub controlled; see notes 1, 2, 3, 4, and 5) parameter symbol timing set unit notes 20 25 35 min max min max min max write cycle time t avav 20 ? 25 ? 35 ? ns 6 address set-up time t avbl 0?0?0?ns address valid to end of write (g high) t avbh 12 ? 15 ? 18 ? ns address valid to end of write (g low) t avbh 15 ? 17 ? 20 ? ns byte pulse width (g high) t bleh t blwh 8 ? 10 ? 15 ? ns byte pulse width (g low) t bleh t blwh 8 ? 10 ? 15 ? ns data valid to end of write t dvbh 5?6?10?ns data hold time t bhdx 0?0?0?ns write recovery time t bhax 8 ? 10 ? 12 ? ns notes: 1. a write occurs during the overlap of e low and w low. 2. due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. if g goes low at the same time or after w goes low, the output will remain in a high-impedance state. 4. after w , e , or ub /lb has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. if both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. 6. all write cycle timings are referenced from the last valid address to the first transition address.
timing specifications MR2A16A/d, rev. 0.1 freescale semiconductor 13 figure 8. write cycle 3 (lb /ub controlled) t avav t bhax a (address) data valid e (chip enable) w (write enable) lb , ub (byte enable) q (data out) d (data in) hi-z hi-z t avbl t bleh t blwh t bhdx t dvbh t avbh
MR2A16A/d, rev. 0.1 14 freescale semiconductor ordering information ordering information ts package (44-lead, tsop type ii, case 924a-02) notes (order by full part number) mr 2 a 16 a ts 25 c freescale mram memory prefix density code (2 = 4 mb, 4 = 16 mb) memory type (a = asynch, s = sync) timing set package type (ts = tsop) revision (a = rev 1) i/o configuration (08 = 8 bits, 16 = 16 bits) commercial device numbers ? MR2A16Ats25c operating temperature range (c = 0 c to 70 c) MR2A16Ats35c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimensions do not include mold protrusion. allowable mold protrusion is 0.15 per side. 4. dimensions do not include dambar protrusions. dambar protrusion shall not cause the lead width to exceed 0.58. b m 0.2 c b a c 44 23 122 1.05 ee 10.29 18.54 42x 4x 44x 0.1 c seating plane 22x 11.96 1.20 max view d 0.15 0.60 0.45 rotated 90 clockwise view d 40 places section e?e 0.21 /2 a m 0.2 c 0.8 3 10.03 3 18.28 0.95 11.56 0.8 0.30 0.12 4 0.05 5 0 0.40
notes MR2A16A/d, rev. 0.1 freescale semiconductor 15 this page is intentionally blank
MR2A16A/d rev. 0.1, 7/2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate ta i po, n . t. h o n g ko n g 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004.

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